A very large number of signal reception architectures are available in the current state of the art for reception of radiofrequency signals. The book <<RF Microelectronics>> by B. RAZAVI describes several types of these architectures.
At the moment, there is a strong demand for the development of simplified reception architectures with low consumption. The purpose is to provide solutions for so-called low speed transmission systems with severe consumption and cost constraints. However, these simplified architectures must be capable of receiving very low amplitude signals particularly so as to obtain an attractive range on wireless transmission systems.
In the special case of pulse UWB systems, new architectures have recently been proposed by work groups: <<Proposals for IEEE 802.15.4a Alternate PHY>>. These architectures are different essentially due to the processing applied to signals in the reception chain and their implementation on silicon. These architectures may be classified into several categories.
So-called <<transmitted reference>> architectures are based on successive emission of a reference pulse and a pulse coding the data to be transmitted. Therefore, the receiver must be capable of making a correlation between the delayed reference pulse and the pulse coding the data to be transmitted. This type of receiver requires integration of a delay cell. In the case of an analog version, the implementation of this delay cell and the correlation cell is relatively complex due to the required precision and the gain control at the input that must be done. In the case of a digital version, processing of the delay and of signals correlation is simplified but management of high speed digital data may prove to be difficult and increase consumption.
Architectures based on the voltage peaks detection or on the detection of fronts are very simple to implement. However, they have limited performances in terms of range because it is difficult to make coherent integrations, in other words to take the average of several received synchronous pulses so as to reduce noise, to increase the signal to noise ratio of the received signals.
Architectures based on a frequency change are attractive because they make it possible to perform a number of processings at lower frequencies. However, they require the integration of a frequency synthesis circuit operating at very high frequency and the gain control at the mixer input is complex.
Energy detection architectures represent an attractive alternative because the implementation scheme is relatively simple. They make it possible to capture all energy present at reception and are compatible with a coherent integration. However, the implementation of these detection circuits in classical silicon technologies is very difficult. The dynamic range obtained on these circuits is usually low. The structure can be made more complex to improve the dynamic range of the energy detector, but at the detriment of frequency performances. The consumption is then higher and the constraint on the gain control circuit is severe.
A simplified receiver architecture was recently proposed in publication <<STMicroelectronics proposal for IEEE 802.15.3a Alternate PHY>> by D. Helal et al. It is based on the principle of 1 bit digitization of the received signal at very high frequency (20 GHz). The design of the first RF stage is simplified, as are gain control constraints. However, considering the high data speed, the complexity and therefore the consumption of the digital part associated with this receiver are high. It is also necessary to make a precise synchronization between the transmitter and the receiver and a good estimate of wave propagation. The digitization frequency of the system can be reduced by sub-sampling the signal but digital processing is still important.